MIXDES - The MIXDES 2005 information

12th International Conference
Mixed Design of Integrated Circuits and Systems
Kraków, 22-25 June 2005

The MIXDES 2005 Conference took place in Kraków, Poland. The topics of the MIXDES Conference included:

  1. Design of Integrated Circuits and Microsystems
  2. Thermal Issues in Microelectronics
  3. Analysis and Modelling of ICs and Microsystems
  4. Microelectronics Technology and Packaging
  5. Testing and Reliability
  6. Power Electronics
  7. Signal Processing
  8. Embedded Systems
  9. Medical Applications
  10. Information Technology
  11. Education

The total number of 180 papers from 31 countries were accepted for publication including 6 invited papers.

The following invited papers were presented during the conference:

  1. Advanced Technologies for Future Direction of Radio Frequency and Wireless Communication, K.J. Johnson (Freescale Semiconductor, USA)
  2. Challenges and Opportunities in Technology Platform Development for Advanced IC Design, Y. Cheng (SiliconLinX Inc., USA)
  3. Fast Methods for Electromagnetic and Circuit-electromagnetic Simulation of Mixed-signal Systems and High-speed ICs in Time and Frequency Domains, V. Jandhyala, S. Chakraborty, D. Gope, C. Yang (University of Washington, USA)
  4. Nano-explosions in Silicon, M. du Plessis (University of Pretoria, SOUTH AFRICA), C. Conradie (African Explosives Limited, SOUTH AFRICA)
  5. Optical Interconnects - A Challenge to Semiconductor Lasers, B. Mroziewicz (Institute of Electron Techn., POLAND)
  6. Three Terminal Optical Sources (450nm - 750nm) for Next Generation Silicon CMOS OEIC's, L. Snyman (Tshwane Univ. of Techn., SOUTH AFRICA), M. du Plessis (University of Pretoria, SOUTH AFRICA), H. Aharoni (Ben Gurion Univ. of the Negev, ISRAEL)

The following special sessions were organised during the conference:

  1. Advanced Compact Modeling and its Standardization
    • 2-D Numerical Modeling of MOSFET Varactors for Application in High-speed Voltage Controled Oscillators, D. Tomaszewski (Institute of Electron Techn., POLAND), L. Lukasiak (Warsaw Univ. of Techn., POLAND), S. Magierowski (University of Calgary, CANADA), K. Iniewski (University of Alberta, CANADA)
    • 3D Electro-thermal Modeling for ESD Protection Devices, H. Xie, R. Zhan, A. Wang (Illinois Institute of Technology, USA)
    • A Compact Model for Future Generation Predictive Technology Modeling and Circuit Simulation, X. Zhou, S.B. Chiah, K. Chandrasekaran, G.H. See, W. Shangguan (Tech. Univ. Singapore, SINGAPORE), S.M. Pandey, M. Cheng, S. Chu, L.-C. Hsia (Chartered Semiconductor Manufacturing Ltd, SINGAPORE)
    • Advanced Device Modeling in Nano-scale and Wireless Era, Y. Cheng (SiliconLinX Inc., USA)
    • An Improved BDJ Verilog-AMS Model Implemented in Cadence Virtuoso Platform for Color Sensor Design, F. Haned, M. Ben Chouikha (Pierre et Marie Curie University, FRANCE), A. Baguenier Desormaux (Cadence Design Systems, FRANCE), G. Alquie (Pierre et Marie Curie University, FRANCE)
    • Challenges of Compact RF-modeling for Deep-submicron RF-CMOS Devices, S. Yoshitomi (Toshiba, JAPAN)
    • Compact Modelling for Surrounding Gate MOSFETs, B. Iniguez, H.A. Hamid (Universitat Rovira i Virgili, SPAIN), D. Jimenez (Universitat Autnnoma de Barcelona, SPAIN), J. Roig (Centro Nacional de Microelectronica, Campus UAB, SPAIN)
    • Empirical MOSFET Modeling for RF Circuit Design, A. Siligaris, G. Dambrine (University of Lille, FRANCE), F. Sischka (Agilent Technologies, GERMANY), F. Danneville (University of Lille, FRANCE)
    • Extraction of EKV Model Parameters Using MOSTXX Application, D. Tomaszewski, A. Malinowski, A. Kociubinski (Institute of Electron Techn., POLAND)
    • Non-quasi-static Analysis with HiSIM, a Complete Surface-potential-based MOSFET Model, T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H.J. Mattausch (Tech. Univ. Hiroshima, JAPAN), T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto (Semiconductor Techn. Academic Research Center, JAPAN)
    • Using VHDL-AMS Based Simulation Technology for the Design and Verification of Mechatronic Systems, T. Heurung (Mentor Graphics, GERMANY)
  2. Special Topics in Emerging Electronics Technologies
    • Advances in Test Technology for High-performance System Interconnects, R.H. Flake, S.-L. Liao, S.J. Wang (The Univ. of Texas at Austin, USA)
    • An Evaluation of Deep-submicron CMOS Design Optimized for Operation at 77K, D. Foty (Gilgamesh Associates, USA)
    • DC Offset Cancellation in Direct Conversion Multistandard Wireless Receivers, S.-B. Park, M. Ismail (Ohio State Univ., USA)
    • Highly Sensitive Wide-dynamic Range Optical Receivers, K. Schneider, H. Zimmermann (Vienna Univ. of Techn., AUSTRIA)
  3. CARE Project Special Session
    • A Neutron Irradiation Device for the Testing of Microelectronic Components to Be Used in the Radiation Environment of High-energy Particle Accelerators at DESY, B. Mukherjee (Deutsches Elektronen-Synchrotron DESY, GERMANY), D. Makowski (Tech. Univ. Lodz, POLAND), A. Kalicki, D. Rybka (Warsaw Univ. of Techn., POLAND), M. Grecki (Tech. Univ. Lodz, POLAND), S. Simrock (Deutsches Elektronen-Synchrotron DESY, GERMANY)
    • A Performance Degradation of the Low Level RF Control System for VUV-FEL, T. Jezynski, M. Grecki (Tech. Univ. Lodz, POLAND)
    • Design and Implementation of Finite State Machine for RF Power Station, B. Koseda, W. Cichalewski (Tech. Univ. Lodz, POLAND)
    • Estimation of IQ Vector Components of RF Field - Theory and Implementation, M. Grecki, T. Jezynski (Tech. Univ. Lodz, POLAND), A. Brandt (Deutsches Elektronen-Synchrotron DESY, GERMANY)
    • From the TESLA Test Facility at DESY to the VUV-FEL User Facility, A. Gamp (Deutsches Elektronen-Synchrotron DESY, GERMANY)
    • Interpretation of the Single Event Upset in Static Random Access Memory Chips Induced by Low Energy Neutrons, B. Mukherjee (Deutsches Elektronen-Synchrotron DESY, GERMANY), D. Makowski (Tech. Univ. Lodz, POLAND), D. Rybka (Warsaw Univ. of Techn., POLAND), M. Grecki (Tech. Univ. Lodz, POLAND), S. Simrock (Deutsches Elektronen-Synchrotron DESY, GERMANY)
    • Performance of Magnetostrictive Elements at LHe Environment, P. Sekalski, M. Grecki (Tech. Univ. Lodz, POLAND), C. Albrecht (Deutsches Elektronen-Synchrotron DESY, GERMANY)
    • Radiation Tolerant System for Neutron Fluence Measurement, D. Makowski, M. Grecki (Tech. Univ. Lodz, POLAND), B. Mukherjee (Deutsches Elektronen-Synchrotron DESY, GERMANY), B. Swiercz (Tech. Univ. Lodz, POLAND), S. Simrock (Deutsches Elektronen-Synchrotron DESY, GERMANY)
    • Recent Advances in RF Control, S. Simrock (Deutsches Elektronen-Synchrotron DESY, GERMANY)
    • Static and Dynamic Properties of Piezoelectric Actuators at Low Temperature and Integration in SRF Cavities Cold Tuning Systems, M. Fouaidy, G. Martinet, N. Hammoudi, F. Chatelet, N. Gandolfo, H. Saugnac, S. Bousson (IPN Orsay, FRANCE), P. Sekalski (Tech. Univ. Lodz, POLAND)
    • System for High Resolution Detection of Beam Induced Transients in RF Signals, P. Pawlik, M. Grecki (Tech. Univ. Lodz, POLAND), S. Simrock (Deutsches Elektronen-Synchrotron DESY, GERMANY)
    • The sCore - Operating System for Research of Fault-tolerant Computing, B. Swiercz, D. Makowski, A. Napieralski (Tech. Univ. Lodz, POLAND)
  4. EDUCHIP Project Special Session
    • An Educational Circuit for Measuring Logic Gate Propagation Delays, G. Jablonski, K. Szaniawski, M. Jankowski (Tech. Univ. Lodz, POLAND)
    • Design Aspects of an On-chip Thermostat Unit for the EDUCHIP Project, G. Masa, Z. Benedek, G. Bognar, D. Szente-Varga (Budapest Univ. of Techn. & Econom., HUNGARY), G. Farkas (MicReD Ltd. and Budapest Univ. of Techn. & Econom., HUNGARY), A. Poppe (Budapest Univ. of Techn. & Econom., HUNGARY)
    • Design of Educational Experiments with Analog Array, O. Antonova, D. Pukneva, E. Manolov, M. Hristov (Tech. Univ. Sofia, BULGARIA)
    • Improving Understanding of Analog Circuits Using Practical Experiments, D. Pukneva, O. Antonova, E. Manolov, M. Hristov (Tech. Univ. Sofia, BULGARIA)
    • Laboratory of Mixed Analog-digital Integrated Circuits, R. Dlugosz, P. Pawlowski, A. Dabrowski (Poznan Univ. of Techn., POLAND)
    • On-chip Resistances and Capacitances Measurement, J. Butas, B. Weber (Slovak Univ. of Techn., SLOVAKIA), V. Ac (Univ. Trencín, SLOVAKIA)
    • Test Access Block: Serial Scan vs. Random Access Scan, Z. Pliva, O. Novak (Tech. Univ. Liberec, CZECH REPUBLIC), K. Siekierska, M. Grodner (Institute of Electron Techn., POLAND)
    • Test Chip for Research and Education, A. Golda, A. Kos (AGH Univ. of Science and Techn., POLAND)
  5. REASON Big Final Event
    • Circuit Modeling of Non-volatile Memory Devices, M. Sadd, R. Rao, R. Muralidhar (Freescale Semiconductor, USA)
    • Electrical Issues in Scaling Advanced SoC to Nanoscale, H. Tenhunen (Royal Institute of Technology, SWEDEN)
    • Long Term Trends for Embedded System Design, A.A. Jerraya (TIMA Laboratory, FRANCE)

The following papers has been awarded:

  • Outstanding Paper Award was presented to:
    • A Bang-Bang PLL Employing Dynamic Gain Control for Low Jitter and Fast Lock Times, M. Chan (University of Queensland, AUSTRALIA), A. Postula (Univ. of Queensland, AUSTRALIA), Y. Ding (Nanosilicon Pty Ltd, AUSTRALIA), L. Jozwiak (Eindhoven Univ. of Tech., THE NETHERLANDS)
    • Analysis of Ion-strike Effects in Deep Submicron CMOS Devices, M. Turowski, A. Raman (CFDRC, USA), M. Mostrom (ATK Mission Research, USA)
    • An Internet Based Interactive Tutorial for the Practice of SystemC Using Only Server Sided Tools, C. Layer, O. Pfander, W. Schlecker, E. Schubert, H.-J. Pfleiderer (University of Ulm, GERMANY)
    • A PLL-Based C-V Converter for a Capacitive, Surface-Micromachined Accelerometer, K. Szaniawski, Z. Kulesza, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Application of RTCP-nets for Design and Analysis of Embedded Systems, M. Szpyrka, T. Szmuc (AGH Univ. of Science and Techn., POLAND)
    • ATM Transmission Controller Implementation in Digital IC, P. Szecowka, M. Burski (Wroclaw Univ. of Techn., POLAND)
    • CMOS Blocks for On-chip RF Test, R. Ramzan (Linkoping University, SWEDEN), J. Dabrowski (Linkoping Univ., Sweden and Silesian University of Techn., POLAND)
    • Data Acquisition System for Silicon Ultra Fast Cameras for Electron and Gamma Sources in Medical Applications, M. Jastrzab, W. Kucewicz, H. Niemiec, M. Sapor (AGH Univ. of Science and Techn., POLAND), A. Czermak, B. Dulny, B. Sowicki, A. Zalewska (Institute of Nuclear Physics, POLAND)
    • Demonstration of an Integrated Digital Circuit Using a Pentacene Organic Transistor Technology, C. Lackner, W. Gut, R. Spilka, A. Tanda, T. Ostermann, R. Hagelauer (JK-University Linz, AUSTRIA), H. Klauk, M. Halik, D. Rhode, F. Eder, U. Zschieschang, G. Schmid, C. Dehm, R. Brederlow (Infineon Technologies, GERMANY)
    • Design Aspects of an On-chip Thermostat Unit for the EDUCHIP Project, G. Masa, Z. Benedek, G. Bognar, D. Szente-Varga (Budapest Univ. of Techn. & Econom., HUNGARY), G. Farkas (MicReD Ltd. and Budapest Univ. of Techn. & Econom., HUNGARY), A. Poppe (Budapest Univ. of Techn. & Econom., HUNGARY)
    • Family of the Even-odd Switched Capacitor Finite Impulse Response Filters, R. Dlugosz, P. Pawlowski, A. Dabrowski (Poznan Univ. of Techn., POLAND)
    • Fully Differential High-speed CMOS Operational Amplifier, F. Schlögl, H. Zimmermann (Vienna Univ. of Techn., AUSTRIA)
    • Modeling of the Impact of Transistor Gate Length Variations on Clock Skew in Buffered H-trees, D. Kasprowicz (Warsaw Univ. of Techn., POLAND)
    • New Architecture of Programmable SC FIR Filter with Circular Memory, R. Dlugosz (Poznan Univ. of Techn., POLAND)
    • Reversible Full Adders Applying Fredkin Gates, Y. Van Rentergem, A. De Vos (Univ. of Ghent, BELGIUM)
    • RF-sampling Mixer for Zero-if Receiver with High Image-rejection, S. Andersson (Linkoping University, SWEDEN), J. Konopacki (Silesian University of Techn., POLAND), J. Dabrowski (Linkoping Univ., Sweden and Silesian University of Techn., POLAND), C. Svensson (Linkoping University, SWEDEN)
    • Scratch Defects In Deep-sub-micron Integrated Circuits, W. Jonca (Warsaw Univ. of Techn., POLAND)
    • STESI: A New Software-based Strategy for Testing SoCs Containing Wrapped IP Cores, M. Tuna, M. Benabdenbi, A. Greiner (Univ. Paris 6, FRANCE)
    • Temperature Measurements on Smart Power ICs during Pulsed Operation, A. Castellazzi, G. Wachutka (Munich Univ. of Techn., GERMANY), M. Honsberg-Riedl (Siemens AG, GERMANY)
    • Testing Mixed-signal Circuits by Supply Current Sensing Using Auto Zero Voltage Comparator, V. Nagy, V. Stopjakova, P. Malosek, L. Majer (Slovak Univ. of Techn., SLOVAKIA)
    • Wideband MCML Basic Cells in 0.35 µm CMOS, R. Ramzan (Linkoping University, SWEDEN), J. Dabrowski (Linkoping Univ., Sweden and Silesian University of Techn., POLAND)


Receipt of papers:

March 1st, 2017

Notification of acceptance:

April 30th, 2017

Registration opening:

May 15th, 2017

Final paper versions:

May 31th, 2017