MIXDES - The MIXDES 2012 information

19th International Conference
Mixed Design of Integrated Circuits and Systems
Warsaw, 24-26 May 2012

The MIXDES 2012 Conference took place in Warsaw, Poland. The topics of the MIXDES Conference included:

  1. Design of Integrated Circuits and Microsystems
  2. Thermal Issues in Microelectronics
  3. Analysis and Modelling of ICs and Microsystems
  4. Microelectronics Technology and Packaging
  5. Testing and Reliability
  6. Power Electronics
  7. Signal Processing
  8. Embedded Systems
  9. Medical Applications
  10. Student Projects

The total number of 117 papers from 32 countries were accepted for publication including 5 invited papers.

The following invited papers were presented during the conference:

  1. Ballistic Transport in Nanoscale Devices, V.K. Arora (Univ. Tekn. Malaysia, MALAYSIA and Wilkes Univ., USA)
  2. Semiconductor Nanowires for Future Electronic Devices, H. Riel (IBM Research - Zurich, SWITZERLAND)
  3. Simulation and Modeling of Nanoscale Multiple-gate SOI MOSFETs, B. Iñíguez (Univ. Rovira i Virgili, SPAIN), R. Ritzenthaler (IMEC, BELGIUM), F. Lime, B. Nae (Univ. Rovira i Virgili, SPAIN)
  4. Transistor and Interconnect Modeling for Design of Carbon Nanotube Integrated Circuits, A. Srivastava (Louisiana State Univ., USA)
  5. Trends and Challenges in Micro- and Nanoelectronics for the Next Decade, C. Claeys (Imec, BELGIUM)

The following special sessions were organised during the conference:

  1. Compact Modeling Support for Nanoscaled IC Technology and Design
    • Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models, F. Javid, R. Iskander (Univ. Pierre and Marie Curie, FRANCE), F. Dusbin (CEA DAM/DIF, FRANCE), M.-M. Louërat (Univ. Pierre and Marie Curie, FRANCE)
    • Analytical Drain Current Core Model for Undoped Double Gate MOS Transistor, P. Sałek, L. Łukasiak, A. Jakubowski (Warsaw Univ. of Techn., POLAND)
    • Analytical Model for Predicting Subthreshold Slope Improvement versus Negative Swing of S-shape Polarization in a Ferroelectric FET, A. Rusu, A.M. Ionescu (EPFL, SWITZERLAND)
    • Characterization of Parameter Variability and Correlations for FD SOI CMOS Technology, D. Tomaszewski, G. Głuszko, J. Malesińska, K. Kucharski (Institute of Electron Techn., POLAND)
    • Compact Modeling Framework for Double-Gate Tunnel FET, U. Monga (Intel Mobile Communications GmbH, GERMANY), N. Goyal (Univ. Graduate Center and Norwegian Univ. of Science and Techn., NORWAY)
    • Impact Ionization Effect in Deep Submicron MOSFET Features Simulation, D. Speransky, T.T. Trung (Belarusian State Univ., BELARUS)
    • KLU Sparse Direct Linear Solver Implementation into NGSPICE, F. Lannutti, P. Nenzi, M. Olivieri (Sapienza - Univ. Roma, ITALY)
    • Simulation Study of Nanoscale Double-Gate CMOS Circuits Using Compact Advanced Transport Models, M. Cheralathan (Univ. Rovira i Virgili, SPAIN), E. Contreras (CINVESTAV, MEXICO), J. Alvarado (Benemérita Univ. Autónoma de Puebla, MEXICO), A. Cerdeira (CINVESTAV, MEXICO), B. Iñíguez (Univ. Rovira i Virgili, SPAIN)
    • Standardization of Multigate MOSFET Modeling, N. Chevillon, F. Prégaldiny, C. Lallement (Univ. Strasbourg, FRANCE), J.-M. Sallese (EPFL, SWITZERLAND)
    • Time-domain Waveform Based Extraction of FinFET Non-linear I-V Model, D. Schreurs, G. Avolio (Univ. Leuven, BELGIUM), A. Raffo, G. Vannini (Univ. Ferrara, ITALY), G. Crupi, A. Caddemi (Univ. Messina, ITALY)
    • Two-dimensional Physics-based Modeling of Dopant-segregated Schottky Barrier UTB MOSFETs, M. Schwarz, T. Holtij (Tech. Hochschule Mittelhessen, GERMANY and Univ. Rovira i Virgili, SPAIN), A. Kloes (Tech. Hochschule Mittelhessen, GERMANY), B. Iñíguez (Univ. Rovira i Virgili, SPAIN)
    • Verilog-A Compact Semiconductor Device Modelling and Circuit Macromodelling with the QucsStuddio-ADMS "Turn-Key" Modelling System, M.E. Brinson (London Metropolitan Univ., UK), M. Margraf (Qucs, GERMANY)
  2. Especial TRAMS (Terascale Reliable Adaptive Memory Systems) Project
    • Enhancing 6T SRAM Cell Stability by Back Gate Biasing Techniques for 10nm SOI FinFETs under Process and Environmental Variations, Z. Jakšić, R. Canal (Univ. Politècnica de Catalunya, SPAIN)
    • Mitigating Lower Layer Failures with Adaptive System Reconfiguration, T. Ramírez, E. Herrero, N. Axelos, J. Carretero, N. Foutris, D. Sanchez, X. Vera (Intel Labs, SPAIN)
    • SRAM Lifetime Improvement by Using Adaptive Proactive Reconfiguration, P. Pouyan, E. Amat, A. Rubio (Univ. Politècnica de Catalunya, SPAIN)
    • Strain Relevance on the Improvement of the 3T1D Cell Performance, E. Amat, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio (Univ. Politècnica de Catalunya, SPAIN)
    • Variability and Reliability Analysis of CNFET in the Presence of Carbon Nanotube Density Fluctuations, C.G. Almudéver, A. Rubio (Univ. Politècnica de Catalunya, SPAIN)
  3. Technologies towards Cognitive Transceivers - Par4CR Project
    • 24 GHz LNA Design in Hybrid Technology, U. Johannsen (Tech. Univ. Eindhoven, THE NETHERLANDS)
    • Advanced Coexistence Technologies for Radio Optimization in Licensed and Unlicensed Spectrum - ACROPOLIS Vision, A. Kliks (Adam Mickiewicz Univ., POLAND)
    • Can Europe Make Use of TV White Spaces - COGEU Project, A. Kliks (Adam Mickiewicz Univ., POLAND)
    • Comparison on Flexible Transceivers Performances, M. Suarez (Institute of Electron Techn., POLAND)
    • Design of a Wideband Low Pass Filter for High Data Rate Application, M. Setu (Catena, SWEDEN)
    • Design of Layout in Sub-micron Technologies, A. Jarosz (Institute of Electron Techn., POLAND)
    • Digital Hardware Resources for Steering a Nonlinear Interference Suppressor, E.J.G. Janssen, H. Habibi, D. Milosevic, P.G.M. Baltus, A.H.M. van Roermund (Eindhoven Univ. of Techn., THE NETHERLANDS)
    • General Aspects of ADC for Multi-standard Radio, S. Ahmad (IMST GmbH, GERMANY)
    • HFB-based Analog to Digital Converters, O. Venard (ESIEE, Paris, FRANCE)
    • Interferer Robust Wide-band Receiver Techniques, B. Nauta (Univ. Twente, THE NETHERLANDS)
    • Introduction - General Presentation of the Par4CR Project, P. Baltus (Tech. Univ. Eindhoven, THE NETHERLANDS)
    • LINC Architecture: A Discussion, E. Habekotté, F. van der Wilt (Catena, THE NETHERLANDS)
  4. xTCA for Instrumentation
    • Development of uTCA Hardware for BAM System at FLASH and XFEL, S.B. Habib, D. Sikora (Warsaw Univ. of Techn., POLAND), J. Szewiński, S. Korolczuk (National Center for Nuclear Research, POLAND)
    • FMC-based Neutron and Gamma Radiation Monitoring Module for xTCA Applications, T. Kozak, D. Makowski, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • Image Acquisition Module for uTCA-based Systems, A. Mielczarek, D. Makowski, G. Jabłoński, P. Perek, A. Napieralski (Tech. Univ. Łódź, POLAND)
    • Image Visualisation and Processing in DOOCS and EPICS, P. Perek, J. Wychowaniak, D. Makowski, M. Orlikowski, A. Napieralski (Tech. Univ. Łódź, POLAND)

The following papers has been awarded:

  • Young Scientists Contest Award was presented to:
    • A Low Noise Low Offset Current Mode Instrumentation Amplifier, A. Voulkidou, S. Siskos, T. Laopoulos (Aristotle Univ. Thessaloniki, GREECE)
  • Poland Section IEEE ED Society Special Award was presented to:
    • A Novel Charge Recycling Approach to Low-Power Circuit Design, C. Ulaganathan, C.L. Britton, Jr., J. Holleman, B.J. Blalock (The Univ. of Tennessee, USA)
  • Outstanding Paper Award was presented to:
    • A Calibratable Capacitance Array Based Approach for High Resolution CR SAR ADCs, J.H. Mueller, S. Strache, L. Busch, R. Wunderlich, S. Heinen (RWTH Aachen Univ., GERMANY)
    • A Hierarchical Algorithm for Moving Vehicle Identification Based on Acoustic Noise Analysis, S. Astapov, A. Riid (Tallinn Univ. of Techn., ESTONIA)
    • A Specific Parameters Analysis of CMOS Hall Effect Sensors with Various Geometries, M.-A. Paun, J.-M. Sallese, M. Kayal (EPFL, SWITZERLAND)
    • Automatisation of Computer-aided Burn Wounds Evaluation, W. Tylman, M. Janicki, A. Napieralski (Tech. Univ. Lodz, POLAND)
    • Combined Hardware and Software Tracing of Real and Virtual Embedded System Parts, C. Koehler (Univ. Siegen, GERMANY), A. Mayer (Infineon Technologies AG, GERMANY), M. Wurm (Univ. Siegen, GERMANY)
    • Compensation of the Temperature Fluctuations in the Silicon Photomultiplier Measurement System, M. Baszczyk, P. Dorosz, S. Głąb, W. Kucewicz, Ł. Mik, M. Sapor (AGH Univ. of Science and Techn., POLAND)
    • Design of an Analog Output Buffer for Active Matrix Displays Using Low-Temperature Polycrystalline Silicon Thin-Film Transistors, I. Pappas, S. Siskos, A.A. Hatzopoulos (Aristotle Univ. Thessaloniki, GREECE)
    • Fractional Delay Filter Design with Extracted Window Offsetting, M. Blok (Gdansk Univ.of Techn., POLAND)
    • SRAM Lifetime Improvement by Using Adaptive Proactive Reconfiguration, P. Pouyan, E. Amat, A. Rubio (Univ. Politècnica de Catalunya, SPAIN)
    • Survey and Analysis of the Design Issues of a Low Cost Micro Power DC-DC Step Up Converter for Indoor Light Energy Harvesting Applications, C. Carvalho (Instituto Politécnico de Lisboa, PORTUGAL), J.P. Oliveira, N. Paulino (Univ. Nova de Lisboa, PORTUGAL)
    • The Effect of Thermal Inertia in Photovoltaic Module Simulation, M. Piotrowicz, W. Marańda (Tech. Univ. Lodz, POLAND)
    • Thermal Models for Dynamic Clock Control, M. Frankiewicz, A. Kos (AGH Univ. of Science and Techn., POLAND)


Receipt of papers:

March 1st, 2017

Notification of acceptance:

April 30th, 2017

Registration opening:

May 15th, 2017

Final paper versions:

May 31th, 2017