Distinguished Lecturer Mini-Colloquium

IEEE ED Poland Chapter informs about a Distinguished Lecturer Mini-Colloquium "Characterization and SPICE Modeling for Nanoscaled IC Designs", which will be held in Bydgoszcz, June 21, 2017.

A program of the seminar:





09:00  - 09:45

Dr. Tohru Mogami (DL), Photonics Electronics Technology Research Association (PETRA), Tsukuba, Japan, e-mail: t-mogami@petra-jp.org

Title: Advanced Silicon photonics device and process technology of photonic integrated circuits for optical interconnect

Abstract: Optical interconnect is an important technology for wide-band and large-capacity data communications. Photonics devices so far have been mainly fabricated by III-V and non-Si materials. This made device integration difficult. Recently, Si photonics technology has been emerging. For optical interconnect, silicon photonics based on Si CMOS technology is a key to produce integrated photonic chips. Silicon photonics technology has advantages of stable device integration on a chip and low-cost with high-speed and large-capacity performance. In this presentation, the silicon photonics technology for optical interconnect will be address from the viewpoint of optical device theory and process techniques. Furthermore, the recent advanced silicon photonics research and development technology by PETRA and other companies will be introduced and a perspective of the future silicon photonics technology will be discussed for advanced photonic integrated circuits. This work is partly supported by NEDO.

09:55  - 10:40

Prof. Henryk Przewłocki (DL) Instytut Technologii Elektronowej, Poland,
e-mail: hmp@ite.waw.pl

Title: Photoelectric characterization of the MIS system. Theory, our contributions and recent advances.

Abstract: In this presentation the “classical” theory of the MIS system photoelectric characteristics will be presented and explained. Some weak points of this theory will be pointed out by comparing its results with experimental data. In particular it will be shown that the theory does not properly predict the photocurrent vs. voltage characteristics of MIS structures, taken at weak electric fields in the insulator. Physical phenomena responsible for that will be explained and appropriate corrections to the theory will be presented as well as practical application of these corrections.

It will also be shown that the classical theory does not account for differences in characteristics of MIS structures with n or p-type substrates. Experimental proof of these differences will be shown together with explanation of the physics underlying this phenomenon. Appropriate corrections to the theory will be discussed and application of these corrections will be presented.

Finally, application results of the novel Grapheme-Insulator-Semiconductor (GIS) test structures in photoelectric characterization of semiconductor devices will be presented and their advantages demonstrated.

A summary of the discussed problems will conclude the presentation.

10.50  - 11:10


11:10  - 11:55

Prof. Benjamin Iñiguez (DL), Universitat Rovira i Virgili (URV), Spain,
e-mail: benjamin.iniguez@urv.cat

Title: Physically-Based Compact Modeling of AlGaN/GaN HEMTs.


12:05  -  12:50

Prof. Mike Brinson London Metropolitan University, UK,
e-mail: mbrin72043@yahoo.co.uk

Title: An outline of Qucs-S compact device modelling: History and capabilities

Part 1: Equation-Defined Device (EDD) modelling to Verilog-A module synthesis.

Abstract: see below

13:00  -  13:40


13:40  -  14:25

Prof. Mike Brinson London Metropolitan University, UK

Title: An outline of Qucs-S compact device modelling: History and capabilities

Part 2: XSPICE Code Models; basic properties to model synthesis, and beyond.

Abstract: The purpose of this two part presentation is to provide the compact device modelling community with a detailed introduction to the history and capabilities of the modelling features implemented in the Qucs-S multi-simulator software package. Roughly ten years ago the Qucs Development Team started the process of adding compact device modelling features to the widely used Qucs circuit simulator. In 2017 the first stable version of the multi-simulator version of Qucs, called Qucs-S, was released. This GPL software package provides users with an extensive range of simulation and modelling tools, including (1) Ngspice, SPICE OPUS and Xyce and (2) subcircuits, non-linear EDD, SPICE B style sources, Verilog-A modules, XSPICE Code Models, SPICE netlist synthesisers, Verilog-A, module and XSPICE Code Model synthesisers. The properties and use of these simulation modelling tools are introduced and their application described with a series of semiconductor device models. The slides from this presentation are intended to be a reference source when developing Qucs-S compact device models. They will be made freely available to Mini-Colloquium delegates via the web.

14:35  -  15:20

Prof. Paweł Gryboś, AGH University of Science and Technology, Poland,
e-mail: pawel.grybos@agh.edu.pl

Title: Noise and mismatch minimization in the design of multichannel integrated circuits.


15:30  -  17:30

Prof. Jim Greer, ASCENT Programme Co-ordinator, Tyndall National Institute (Ireland) http://www.ascent.network/, e-mail: jim.greer@tyndall.ie

Title: ASCENT: Access to European Nanoelectronics Infrastructure

Abstract: ASCENT is a European Infrastructure access programme which brings together imec (Belgium), Leti (France) and Tyndall (Ireland).

ASCENT provides fast and easy access to the world’s most advanced CMOS nanoelectronics data and test structures in Europe’s leading nanofabrication research institutes. ASCENT offers 14nm CMOS (FDSOI and finFET) device data, nanoscale test chips and electrical/physical characterisation facilities.

ASCENT enables Europe’s world-leading TCAD and compact modelling community to perform the systematic studies that are required to develop nanoscale design methodologies and to identify the impact of quantum effects on sub-20nm device performance. As part of the ASCENT offer, the TCAD and compact modelling community has OPEN ACCESS to 14nm PDKs and electrical characterisation data through the ASCENT Virtual Access (VA) service.

A number of Case Studies will show the experience of existing VA users and how they have benefitted from it.


The seminar will be dedicated to the students, engineers and researchers working in the field of silicon-based micro- and nanoelectronics: technology/device modeling and characterization, device/integrated circuit design. The seminar will be open for a wide audience.

The seminar will be organized by IEEE ED Poland Chapter, Instytut Technologii Elektronowej (ITE), Warsaw, Poland and Department of Microelectronics and Computer Science (DMCS), Łódź University of Technology, Łódź, Poland.

The seminar location: City Hotel, ul. 3 Maja 6, 85-950 Bydgoszcz

The seminar program and other related information will be updated accordingly.


Receipt of papers:

February 28th, 2018

Notification of acceptance:

April 30th, 2018

Registration opening:

May 15th, 2018

Final paper versions:

May 15th, 2018